One of the main barriers to achieving lower energy CMOS (complementary metal oxide semiconductor) logic is the difficulty in lowering the supply voltage. The supply voltage is constrained by the sub-threshold swing, which is limited by Fermi-Dirac statistics to 60 mV/decade at room temperature. In particular, it is known that with a conventional field effect transistor, a change in the channel potential of at least 60 mV at 300 K is needed to cause a change in the current by a factor of 10. This minimum sub-threshold slope results in a fundamental lower limit on the operating voltage for conventional FET semiconductor switches.